Arrhenius Solid State Diffusion Parameters for Lead Free PCB Surface Finishes

Interface

Solid-state atom migration occurs across lead-free surface finishes whenever thermal energy acts on the interface between copper traces and deposited metallic coatings. This movement drives intermetallic compound growth from room-temperature storage through reflow, bake cycles, and high-temperature operation. The atomic flux follows Arrhenius kinetics, where diffusion coefficient D scales exponentially with absolute temperature T in Kelvin, based on pre-exponential frequency factor D0 and activation energy Ea against universal gas constant R (8.314 J/mol·K):

D(T) = D0 · expleft(-fracEaR · Tright)

Intermetallic layer thickness x increases over dwell time t following parabolic kinetics where x = sqrtD · t or x2 = x02 + 2 · k · t, with k as the reaction rate constant. Different surface finishes present distinct diffusion couples, creating specific intermetallic structures and kinetic parameters. Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), Immersion Tin, Immersion Silver, and Lead-Free Hot Air Solder Leveling (HASL) each form unique interface boundaries that dictate solderability retention and mechanical joint fatigue.

Activation energy determines thermal sensitivity. Immersion Tin over bare copper has a low activation energy of 79.1 kJ/mol for Cu6Sn5 formation, which quickly consumes surface tin at 40circC storage or during standard preheating. Above 100circC, a secondary Cu3Sn phase forms at the copper interface with an activation energy of 103.4 kJ/mol.

This higher barrier keeps Cu3Sn growth negligible at room temperature, though it becomes the primary phase during burn-in testing and automotive engine-compartment operation.

These diffusivity values directly influence assembly yields and storage lifetimes, making them essential when setting shelf-life limits or wave soldering profiles. Once available tin converts entirely into intermetallics, thin deposits expose the copper underneath and eliminate wetting during SMT reflow.

Layer

Plated deposits serve as physical barriers, slowing atomic migration between copper tracks and solder joints. In ENIG finishes, electroless nickel co-deposited with 7 to 10 percent phosphorus by weight limits rapid copper dissolution. The gold topcoat (0.025 to 0.05,μm) exists only to prevent nickel oxidation and dissolves into molten solder within two seconds of reflow, exposing the nickel-phosphorus layer directly to liquid solder.

Under elevated thermal aging, nickel atoms diffuse outward into tin to form crystalline Ni3Sn4, expelling co-deposited phosphorus into adjacent unreacted nickel to form an amorphous Ni3P barrier layer.

Phosphorus concentrations dictate structural changes at the interface. As nickel migrates toward tin, phosphorus accumulates at the intermetallic front, creating a thin, brittle phosphorus-rich deposit (Ni3P) and a hyper-phosphorus phase (NixP). This transformation lowers shear strength during high strain rate events like drop testing or thermal shock.

Content below 6 percent accelerates nickel diffusion and intermetallic growth, whereas content above 10.5 percent induces stress and promotes hyper-corrosion during gold immersion ~ the condition known on shop floors as black pad.

Phosphorus Accumulation and ENEPIG Palladium Dynamics

Adding an electroless palladium layer (0.05 to 0.15,μm) between nickel and gold creates the ENEPIG structure, suppressing atomic flux. Palladium slows nickel dissolution into molten solder, shifting growth from binary Ni3Sn4 to ternary (Pd,Ni)Sn4 and (Ni,Pd)3Sn4 phases. Higher activation energy for diffusion through the palladium barrier (84.2 kJ/mol) reduces intermetallic growth speed to under one-third that of standard ENIG at 125circC.

Immersion Tin omits barrier layers entirely, placing tin directly against copper. Diffusion across this boundary is fast: copper moves into tin quicker than tin into copper, creating an imbalanced mass transport flux. The resulting asymmetry produces localized tensile stress within the tin layer, driving whisker growth that short-circuits fine-pitch components.

• Phosphorus Content Control ~ Maintaining bath phosphorus between 7.5 and 9.0 percent weight suppresses brittle Ni3P phase growth during secondary reflow operations.
• Palladium Thickness Window ~ Depositing 0.08 to 0.12,μm of palladium prevents full dissolution during SMT reflow while preventing brittle PdSn4 needle precipitation in solder joints.
• Immersion Tin Thickness Floor ~ Applying a minimum of 1.0,μm pure tin ensures at least 0.4,μm unreacted metallic tin remains after six months of storage at 30circC and 60 percent relative humidity.
• Immersion Silver Barrier Mechanism ~ Metallic silver dissolves completely into solder matrix, leaving a direct Cu-Sn boundary that grows Cu6Sn5 intermetallics during thermal cycling.

Thin gold layers do not protect underlying nickel from diffusion indefinitely. Floor inspections show that immersion gold contains micro-porosity through which atmospheric oxygen reaches nickel, or through which tin diffuses during warm storage, rendering solderability claims based on gold thickness alone invalid.

Diffusivity

Atomic transport through solid lattices occurs via bulk interstitial vacancies and grain boundaries. Below 100circC, grain boundary migration dominates because disorganized boundaries require less energy to navigate than the ordered lattice matrix. Above 125circC, lattice volume diffusion takes over, altering overall intermetallic growth rates.

Isothermal Intermetallic Growth Model Assumptions

Predicting intermetallic growth across finishes requires fixed baseline assumptions. For a bare copper substrate coated with 1.2,μm Immersion Tin stored at 125circC (398.15 K), the diffusion coefficient for copper into tin is 1.02 × 10-15 m2/s. Total intermetallic growth (Cu6Sn5 + Cu3Sn) follows parabolic kinetics starting from an initial reflow thickness x0 of 0.3,μm.

The total intermetallic thickness x(t) after exposure time t = 1000 hours (3.6 × 106 seconds) is calculated as follows:

x(t) = sqrtx02 + 2 · k · t

x(1000 h) = sqrt(0.3 × 10-6 m)2 + 2 · (1.02 × 10-15 m2/s) · (3.6 × 106 s)

x(1000 h) = sqrt9.0 × 10-14 + 7.344 × 10-9 = sqrt7.34409 × 10-9 m2 ≈ 2.71,μm

Subtracting the initial 0.3,μm leaves 2.41,μm of new intermetallic growth. Stoichiometric calculations show that 1.0,μm of Cu6Sn5 consumes roughly 0.84,μm of surface tin. Forming 2.41,μm of intermetallic requires 2.02,μm of tin ~ exceeding the initial 1.2,μm deposit.

Available tin is consumed well before 1000 hours at 125circC, exposing intermetallics directly to air and destroying solderability.

Kirkendall Void Nucleation Kinetics

Imbalanced diffusion fluxes create microstructural defects. In the Cu-Sn system, copper diffuses into Cu6Sn5 faster than tin moves inward toward copper (DCu > DSn). This outward flux leaves excess atomic vacancies behind at the Cu-Cu3Sn interface.

Once vacancy concentration exceeds equilibrium, the voids coalesce into Kirkendall voids.

Does Palladium Thickness Arrest Intermetallic Growth Rates?

Increasing palladium thickness in ENEPIG beyond 0.2,μm slows nickel intermetallic growth, but introduces mechanical risks. Concentrated palladium forms brittle PdSn4 plates during reflow, which migrate into the bulk solder and act as stress risers under shock loading.

Suppressing grain boundary diffusion without compromising solder joint shear resistance remains a persistent challenge in board reliability engineering.

Incubation

Thermal exposure during storage, transit, and SMT reflow accumulates irreversibly in finish materials. Uncontrolled warehouse storage in humid tropical climates accelerates low-temperature diffusion; nine months at 35circC and 80 percent relative humidity consumes up to 0.5,μm of surface tin on Immersion Tin finishes, altering solderability before assembly even begins.

Reflow Thermal History and Intermetallic Multiplication

Double-sided assembly subjects surface finishes to repeated thermal cycles. Peak reflow temperatures of 245circC to 260circC melt SAC305 solder, driving liquid dissolution rates four orders of magnitude faster than solid-state diffusion. At these temperatures, liquid tin dissolves copper faster than 0.1,μm/second.

On cooling, intermetallics solidify into scallop-shaped Cu6Sn5 crystals. Subsequent reflow passes reheat these structures to 250circC, flattening the scallops into planar layers and pushing copper inward to form Cu3Sn. Each pass adds 0.2 to 0.4,μm to the intermetallic layer, reducing the pure tin available for component lead wetting.

IPC-4552B specifies that mean electroless nickel deposit thickness must remain between 3.0 and 6.0,μm, with gold thickness held strictly between 0.05 and 0.10,μm to prevent severe mechanical embrittlement.

Environmental Aging and Solderability Degradation

As intermetallics consume surface metals, finishes lose protection. Immersion Silver does not form thick intermetallics during room storage, but silver atoms react along sulfur pathways to form Ag2S tarnish, which acts as a thermal barrier during soldering. Organic Solderability Preservatives (OSP) oxidize under repeated reflow passes, breaking down organometallic polymers and exposing copper to air.

Ignoring diffusion rates when setting PCB inventory expiration policies leads to un-solderable boards, higher scrap rates, lost line time, rework costs, and latent field failures from brittle interface fractures.

Screening

Verifying diffusion control requires systematic testing of incoming boards and completed assemblies. Standard X-ray Fluorescence (XRF) measures coating thickness but cannot evaluate diffusion phases, grain boundaries, or thin intermetallic layers. Full evaluation requires micro-sectioning combined with high-resolution Scanning Electron Microscopy (SEM) and Energy Dispersive Spectroscopy (EDS).

Laboratory Cross-Sectioning and SEM/EDS Diagnostics

Cross-section analysis demands careful sample preparation so soft tin or gold does not smear over hard intermetallics. Polishing relies on diamond suspensions down to 0.05,μm, followed by light chemical etching (typically 1 percent nitric acid in ethanol) to expose grain boundaries and phase interfaces.

SEM imaging at 5,000× to 20,000× allows direct measurement of intermetallic thickness, differentiation of scallop from planar morphology, and detection of Kirkendall voids. EDS line scans across the joint trace copper, nickel, tin, phosphorus, and palladium levels, verifying that phosphorus at ENIG interfaces remains within safe limits.

Ball Shear and Mechanical Joint Testing Protocols

Mechanical testing assesses joint integrity under physical strain. High-speed ball shear testing (1.0 to 4.0 m/s per JESD22-B117) reveals brittle-to-ductile fracture behavior. While low-speed shear can mask embrittlement by cutting through soft bulk solder, high-speed shear forces failure along intermetallic interfaces, exposing weak Ni3P layers or Kirkendall voids.

1. Confirm plating thickness on incoming PCB batches using calibrated XRF per IPC-4552B, recording gold, palladium, and nickel values across five test points per panel.
2. Solder sample SAC305 test spheres to dedicated test coupons using standard reflow profiles with peak temperatures held at 245circC ± 3circC.
3. Subject test samples to accelerated isothermal aging at 150circC for 168 hours inside a dry nitrogen storage oven.
4. Execute high-speed ball shear tests at 3.0 m/s impact velocity, recording peak force to failure and failure mode distribution.
5. Accept batches only when ductile force modes exceed 95 percent of test samples, with zero total brittle fractures along intermetallic interfaces.

Under standard IPC-6012 Class 3 supply agreements, any incoming, un-reflowed PCB lot with intermetallic thickness over 0.8,μm is subject to rejection at the supplier’s expense.

Liability

Solid-state diffusion failures often surface months after assembly as field warranty returns. Latent failures from Kirkendall voiding or phosphorus embrittlement disrupt field operation, and isolating root causes requires separating bare PCB plating parameters from reflow thermal history.

Commercial Risk Allocation and Warranty Defensability

Cross-border supply agreements must clearly define solid-state degradation boundaries. Warranty disputes over aged boards generally turn on whether joint failure stemmed from improper warehouse storage and excessive reflow heat, or from thin initial coatings and contaminated plating baths.

Resolving claims depends on maintaining complete thermal records from fabrication through assembly. Board fabricators must provide lot-specific coating thickness records, phosphorus analysis, and micro-section reports with each shipment. Assemblers need to log storage conditions and reflow profiles for every SMT run.

A clear rule of thumb for cross-border electronics procurement is that bare boards with Immersion Tin finishes should be assembled within ninety days of plating, while ENIG and ENEPIG finishes maintain solderability for up to three hundred sixty-five days when stored below thirty degrees Celsius and sixty percent relative humidity.

When intermetallic embrittlement causes field failures, liability depends on whether original manufacturing parameters met specification. If bare board plating complied with IPC thickness standards but assembly exposed boards to three reflow passes and extended burn-in, responsibility lies with the assembler. If plating logs reveal phosphorus above 10 percent or gold under 0.03,μm, replacement, scrap, and rework costs fall back on the fabricator.

Managing shelf life through FIFO stock rotation and strict incoming testing keeps latent intermetallic defects out of finished products, protecting operational budgets and long-term field reliability.